1. Field of the Invention
The invention relates to a non-volatile memory, and particularly relates to a non-volatile memory apparatus and an operation method thereof.
2. Description of Related Art
FIG. 1 is a circuit schematic diagram of a flash memory. The flash memory shown in FIG. 1 includes a plurality of flash memory cells, for example, flash memory cells FC_1_1, . . . , FC_1_m, . . . , FC_n_1, . . . , FC_n_m shown in FIG. 1. Gates of the flash memory cells FC_I_1-FC_n_m are respectively coupled to one of a plurality of word lines WL_1, . . . , WL_m, drains of the flash memory cells FC_I_1-FC_n_m are respectively coupled to one of a plurality of bit lines BL_1, . . . , BL_n, and sources of the flash memory cells FC_1_1-FC_n_m are respectively coupled to a common source line CSL, as shown in FIG. 1.
A programming voltage generator circuit 110 provides a programming voltage VP to a column decoder 120 during a programming period. The column decoder 120 may selectively transmit the programming voltage VP to one of the bit lines BL_1-BL_n. A row decoder 130 may transmit different word line voltages to the word lines WL_1-WL_m through word line drivers 140_1, . . . , 140_m, so that the row decoder 130 and the word line drivers 140_1-140_m may selectively drive one of the word lines WL_1-WL_m. Based on an addressing operation of the column decoder 120 and the row decoder 130, any flash memory cell in the flash memory cells FC_1_1-FC_n_m can be programmed without influencing other flash memory cells.
A voltage switch (or voltage swing) of the word lines WL_I-WL_m is a word line high voltage to a ground voltage. When the voltage of one word line in the word lines WL_1-WL_m is the word line high voltage (i.e. the flash memory cells connected to one of the word lines are selected), the voltage of the other word lines in the word lines WL_1-WL_m is the ground voltage (i.e. the flash memory cells connected to the other word lines are not selected). In view of a single bit line (for example, the bit line BL_1, and the other bit lines can be deduced), when the programming voltage VP is applied to the bit line BL_1, a large amount of leakage current is leaked to the common source line CSL from the bit line BL_1 through the non-selected flash memory cells. The leakage current mainly comes from a sub-threshold current of the flash memory cells (transistors). The more the flash memory cells connected to the bit line BL_1 are, the larger the leakage current of the bit line BL_1 is. The large amount of leakage current may pull down a level of the programming voltage VP to cause an error of the programming operation performed to the flash memory cell.